Search - vhdl controller

[Other] ref-sdr-sdram-verilog

Description: sdram控制器的开发程序，还有文档，可以参考以下-SDRAM controller development process, there is a document, you can refer to the following
Platform: | Size: 776192 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: DDR控制器已通过FPGA 验证大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Platform: | Size: 52224 | Author: kin | Hits:

Description: SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck-SD card controller can just read data using 1 bit SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck
Platform: | Size: 8192 | Author: tuya | Hits:

[VHDL-FPGA-Verilog] dianti

Description: 该程序实现的功能是：基于VHDL语言的电梯控制器-The realization of the program s function is: Based on the VHDL language elevator controller
Platform: | Size: 1024 | Author: 苗黄 | Hits:

[VHDL-FPGA-Verilog] tft_cntlr_ref_v1_00_c

Description: TFT LCD 控制器的VERILOG 源代码程序,已在某项目上成功应用.-TFT LCD controller VERILOG source code procedures have been in a successful application projects.
Platform: | Size: 15360 | Author: liubing | Hits:

[VHDL-FPGA-Verilog] diantikongzhiqi

Description: 本设计是本人的课程设计，基于VHDL的电梯控制器的设计，能够实现12层电梯控制，上下开关，关门延时，提前关门，状态显示，通过波形仿真进行观看结果-The design is my curriculum design, VHDL-based elevator controller design, can achieve 12-storey elevator control, up and down switch, closing delay, early closing, the status display, through to watch the results of waveform simulation
Platform: | Size: 68608 | Author: polly | Hits:

[VHDL-FPGA-Verilog] PicoBlaze_amp_adc

Description: PicoBlaze 处理器放大器和 A/D 转换器控制器展示了 Linear Technology LTC6912-1 可编程增益放大器和 Linear Technology LTC1407A 模数（A/D）转换器的基本操作。结果如字符 LCD 屏幕所示。利用 PicoBlaze 处理器控制器与放大器、A/D 转换器和 LCD 屏幕进行基于 SPI 的通信。-PicoBlaze processor amplifier and A/D converter controller demonstrated the Linear Technology LTC6912-1 programmable gain amplifiers, and Linear Technology LTC1407A modulus (A/D) converter basic operation. The result was as shown in character LCD screen. Use PicoBlaze processor controller and amplifier, A/D converter and SPI-based LCD screen communication.
Platform: | Size: 1906688 | Author: andy qe | Hits:

[VHDL-FPGA-Verilog] lift

Description: 采用vhdl语言的电梯控制器源代码，能够实现报警，等待，并采用了标准的最优电梯运动路线。-Using VHDL language elevator controller source code, to realize the police, waiting, and the optimal use of the standard line of lift movement.
Platform: | Size: 2048 | Author: wriuwru | Hits:

[VHDL-FPGA-Verilog] 61EDA_C52

Description: 标准SDR SDRAM控制器参考设计，有助于大家学习和参考-Standard SDR SDRAM controller reference design will help everyone to learn and reference
Platform: | Size: 205824 | Author: 王廷龙 | Hits:

[VHDL-FPGA-Verilog] mymul

Description: 这是一段用VHDL语言编写的程序用FPGA实现模糊控制器-This is a language with VHDL procedures realize the fuzzy controller using FPGA
Platform: | Size: 1024 | Author: 林 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于FPGA的uart控制器，波特率可选，VHDL编程，Quartusii 6.0 平台，vhdl语言编程-FPGA-based UART controller, an optional baud rate, VHDL programming, Quartusii 6.0 platform, vhdl language programming
Platform: | Size: 5093376 | Author: 吕常智 | Hits:

[ARM-PowerPC-ColdFire-MIPS] rong

Description: 一个IIC总线的代码，一个VGA显示文字代码，目前VGA可以显示彩条，但是现实文字较少，一个本科学生兰编写，还不错，共享下，大家参考，IIC编写的比较经典，可以学习怎么写一个处理器的外设控制器。-IIC bus is a code, a VGA display text code, the current color VGA displays, but less realistic characters, a lan to prepare undergraduate students, but also good to share, the U.S. reference, IIC comparison prepared classics, can learn how to write a processor peripheral controller.
Platform: | Size: 1773568 | Author: rong | Hits:

[VHDL-FPGA-Verilog] clr_m

Description: 用FPGA实现的模糊控制器部分用VHDL编写的源程序-Using FPGA to achieve some of the fuzzy controller using VHDL source code prepared
Platform: | Size: 1024 | Author: 林 | Hits:

[VHDL-FPGA-Verilog] div16_8

Description: 用FPGA实现模糊控制器部分用VHDL语言编写的源程序-Realize the fuzzy controller with FPGA using VHDL language part of the source
Platform: | Size: 1024 | Author: 林 | Hits:

[VHDL-FPGA-Verilog] 18

Description: VHDL语言编写的脉冲控制器实例模块-VHDL language examples pulse controller module
Platform: | Size: 6144 | Author: 王洪亮 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram test controller altera -sdram test controller altera
Platform: | Size: 1519616 | Author: yangchun | Hits:

[Com Port] b13c_environment

Description: rs232控制器，实现rs232的环境设置，verilog编写，所有权归opencores-rs232 controller rs232 to achieve the environmental settings, verilog prepared, owned by opencores
Platform: | Size: 63488 | Author: uknow | Hits:

[VHDL-FPGA-Verilog] oc_i2c_master

Description: 用VHDL制作的I2C控制器，是一个component,之间添加就可以使用。-VHDL produced using I2C controller, is a component, you can use to add between.
Platform: | Size: 386048 | Author: 辛小怡 | Hits:

[Other] fpga_mac_vhdl

Description: 针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入 -Embedded systems for the bottom of this paper, a network interface from FPGA to achieve the Ethernet controller design method. The controller will support the 10Mbps and 100Mbps transfer rate, as well as half-duplex and full-duplex mode, at the same time provides MII interface, and through external Ethernet physical layer (PHY) chip to achieve network access
Platform: | Size: 316416 | Author: 林大朋 | Hits:

[Picture Viewer] VGAcontroler_for_Sopc_Builder

Description: altera公司的sopc builder VGA 控制器设计-altera company sopc builder VGA controller design
Platform: | Size: 94208 | Author: Morgan | Hits:

« 1 2 ... 4 5 6 7 8 910 11 12 13 14 ... 46 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list